Technology ID
TT-0046
Description
High5 Semiconductor develops low-power, high-bandwidth optical interconnect chipsets designed to solve the “memory wall” and power bottlenecks in AI data centers. The core technology utilizes a Co-Packaged Optics (CPO) approach, which enables transparent PCIe and CXL protocol transmission over optical fiber, extending interconnect distances up to 100 meters (across-rows) while achieving industry-leading energy efficiency.
Content
Industry-Leading Energy Efficiency: Our DSP-free architecture eliminates the most power-consuming block in the transceiver. This results in a drastic reduction in power (pJ/bit), directly addressing the critical thermal challenges in high-density AI racks
Ultra-Low Latency: By removing the digital processing bottleneck, our chips process signals in the analog domain, offering significantly lower latency than traditional DSP-based solutions. This is crucial for the performance of parallel AI computing
Cost-Effective & Scalable: Our simplified circuit architecture reduces chip area and complexity. This translates to lower manufacturing costs and higher reliability, making it an ideal solution for mass deployment in next-generation data centers
Inventors
Applicable Industries
Potential Application
Technology Focus
TRL
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