Technology ID
TT-0017
Description
Design automation and optimization for high-performance deep learning accelerators based on many-cores architecture. – Algorithm-Toolchains-Hardware co-design and co-optimization – Hierarchical NAS-DSE co-optimization – Compilation and scheduling mechanism based on dynamic instruction level parallelism – NoC resource contention aware architectural simulation
Content
Reduce many-cores architecture design cycle by about 70%
Significantly reduced architecture design resources required by ~80%
Improved IC power, performance, and area ratio (PPA) by ~30%
Inventors
Applicable Industries
Potential Application
Technology Focus
TRL
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